In a known way, and as illustrated schematically in FIG. 1, a non-volatile memory device, designated by 1, for example of a flash type, generally comprises a memory array 2 made up of a plurality of memory cells 3, arranged in rows (usually defined as wordlines, WL), and columns (usually defined as bitlines, BL).
Each memory cell 3 is constituted by a storage element, for example formed by a floating-gate transistor in flash memories, with gate terminal designed to be coupled to a respective wordline WL, a first conduction terminal designed to be coupled to a respective bitline BL and a second conduction terminal connected to a reference potential (for example ground, gnd). In particular, the gate terminals of the memory cells 3 of a same wordline WL are connected together.
A reading circuit 4 (represented schematically in FIG. 1) enables selection, on the basis of address signals received at the input (generated in a known manner and designated in general by AS), of the memory cells 3, and in particular of the corresponding wordlines WL and bitlines BL each time addressed, enabling biasing thereof at appropriate voltage and current values during the operations of reading of the data stored.
The reading circuit 4 provides in particular a reading path, which is designed to create a conductive path between the bitlines BL of the memory array 2 each time selected and a sense-amplifier stage, of a differential type, designed to compare the current circulating in the addressed (i.e., activated) memory cell 3, which receives an appropriate biasing voltage on the respective gate terminal, with a reference current, in order to determine the value of the datum stored and consequently generate a digital reading signal, indicative of the datum stored.
A reading circuit 4, of a known type, thus envisages in general, as illustrated schematically in FIG. 2, a sense-amplifier stage, designated by 6, having: a first differential input 6a, coupled to a memory cell 3 (to the gate terminal of which an appropriate row-biasing voltage VWL is supplied), from which it receives a cell reading current Icell, the value of which is a function of the datum stored; a second differential input 6b, coupled to a reference circuit element 8, from which it receives a reference current Iref; and an output 6c that supplies a digital output signal Sout, the value of which is a function of the comparison between the cell reading current Icell and the reference current Iref, and is indicative of the value of the datum stored in the memory cell 3, activated for reading the same datum.
In known solutions, the aforesaid reference circuit element 8 may for example be: a reference cell 8a, which is structurally the same as the memory cell 3 that is to be read and has electrical characteristics controlled and known beforehand (for supplying a known value of the reference current Iref); or else a reference-current generator 8b, designed to generate the same reference current Iref, of a desired value.
The reading operation of the datum stored in the memory cell 3 thus envisages detection of the cell reading current Icell and its comparison with the reference current Iref, in order to generate, via the sense-amplifier stage 6, the digital output signal Sout. For instance, in the case where the cell reading current Icell is higher than the reference current Iref, the digital output signal Sout may have a high logic value, ‘1’; whereas the digital output signal Sout may have a low logic value, ‘0’, in the opposite case, where, that is, the cell reading current Icell is lower than the reference current Iref.
The present Applicant has realized that the solutions of a known type for carrying out reading of the data stored in the memory cells of non-volatile memory devices may not be compatible with the requirements of size reduction (the so-called “scaling down”) of memory cells, and of simultaneous increase in electrical performance (in particular, in terms of increase in reading speed, or likewise of reduction of the access time and consumption), envisaged by technological progress.